DSP Processor Architecture and Applications Detailed Syllabus for Control Engineering/ Control Systems M.Tech first year first sem is covered here. This gives the details about credits, number of hours and other details along with reference books for the course.
The detailed syllabus for DSP Processor Architecture and Applications M.Tech 2017-2018 (R17) first year first sem is as follows.
M.Tech. I Year I Sem.
Prerequisite: Microprocessor and its applications
Course Objectives:
- To introduce various techniques of digital signal processing that are fundamental to various industrial applications.
- To learn the basis of DSP systems, its theory and practical implementation of different kind of algorithms
- To know third generation DSP architectures and interfacing of memory and I/O peripherals to the DSP processors.
Course Outcomes: After completion of this course the student
- Gets an in depth knowledge of DSP processors their architectures.
- Knows programming language techniques, integration of DSP programmable devices with memories and I/O peripherals.
UNIT-I: Introduction to Digital Signal Processing: Introduction, A Digital signal-processing system, The sampling process, Discrete time sequences, Discrete Fourier Transform(DFT) and Fast Fourier Transform(FFT),Linear time-invariant systems, Digital filters, Decimation and interpolation, Analysis and Design tool for DSP Systems MATLAB,DSP using ATLAB. Computational Accuracy in DSP Implementations: Number formats for signals and coefficients in DSP systems, Dynamic Range and Precision, Sources of error in DSP implementations, A/D Conversion errors, DSP Computational errors, D/A Conversion Errors, Compensating filter.
UNIT-II: Architectures for Programmable DSP Devices: Basic Architectural features, DSP computational Building Blocks, Bus Architecture and Memory, Data Addressing Capabilities, Address Generation Unit, Programmability and Program Execution, Speed issues Features for External interfacing. EXECUTION CONTROL AND PIPELINING: Hardware looping, Interrupts, Stacks, Relative Branch Support, Pipelining and performance, Pipeline Depth, Interlocking, Branching effects, interrupt effects, pipeline Programming models.
UNIT-III: Programmable Digital Signal Processors: Commercial Digital signal-processing Devices, Data Addressing modes of TMS320C54XX DSPs, Data Addressing modes of TMS320C54XX Processors, Memory space of TMS320C54XX Processors, Program Control, TMS320C54XX instructions and Programming, On-Chip peripherals, Interrupts of TMS320C54XX processors, Pipeline Operation of TMS320C54XX Processors.
UNIT-IV: Implementation of Basic DSP Algorithms: The Q-notation, FIR Filters, IIR Filters, interpolation Filters, Decimation filters, PID Controller, Adaptive Filters, 2-D Signal Processing. Implementation of FFT Algorithms: An FFT Algorithm for DFT Computation, A Butterfly Computation, Overflow and scaling, Bit reversed index generation, An 8-point FFT implementation on the TMS320C54XX, Computation of signal spectrum.
UNIT-V: Interfacing Memory and I/O Peripherals to Programmable DSP Devices: Memory space organization, External bus interfacing signals, Memory interface, parallel I/O interface, Programmed I/O, Direct Memory access(DMA).A Multichannel buffered serial port (McBSP), McBSP Programming, a CODEC interface circuit, CODEC programming, A CODEC-DSP interface example.
TEXT BOOKS:
- S. Salivahanan, A. Vallavaraj. C. Gnanpriya, Digital signal processing -TMH-2nd, 2001.
- Lourens R Rebinarand Bernold, Theory, and applications of digital signal processing.
- Auntoniam, Digital filter analysis and design -TMH.
REFERENCE BOOKS:
- Sanjit K. Mitra, Digital signal processing – TMH second edition
- Lan V. Opphenheim, Ronald W. Shafer, Discrete time signal processing -PHI 1996 1st edition.
- John G. Proakis, Digital signal processing principles – algorithms and applications -PHI-3rd edition 2002.
For all other M.Tech 1st Year 1st Sem syllabus go to JNTUH M.Tech Control Engineering/ Control Systems 1st Year 1st Sem Course Structure for (R17) Batch.
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