Computer Architecture detailed Syllabus for Electrical & Electronics Engineering (EEE), R18 regulation has been taken from the JNTUH official website and presented for the students affiliated to JNTUH course structure. For Course Code, Subject Names, Theory Lectures, Tutorial, Practical/Drawing, Credits, and other information do visit full semester subjects post given below. The Syllabus PDF files can also be downloaded from the universities official website.
For all the other EEE 3rd Year 1st Sem Syllabus for B.Tech R18 Regulation JNTUH, visit Electrical & Electronics Engineering 3rd Year 1st Sem R18 Scheme.
For all the (Professional Elective-I) subjects refer to Professional Elective-I Scheme. The detail syllabus for computer architecture is as follows.
Pre-requisite:
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Course Objectives:
- To understand basic components of computers.
- To understand the architecture of 8086 processor.
- To understand the instruction sets, instruction formats and various addressing modes of 8086.
- To understand the representation of data at the machine level and how computations are performed at machine level.
- To understand the memory organization and I/O organization.
- To understand the parallelism both in terms of single and multiple processors.
Course Outcomes:
At the end of this course, students will demonstrate the ability to
- Understand the concepts of microprocessors, their principles and practices.
- Write efficient programs in assembly language of the 8086 family of microprocessors.
- Organize a modern computer system and be able to relate it to real examples.
- Develop the programs in assembly language for 80286, 80386 and MIPS processors in real and protected modes.
- Implement embedded applications using ATOM processor.
Unit I
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Unit II
Memory Organization System memory, Cache memory – types and organization, Virtual memory and its implementation, Memory management unit, Magnetic Hard disks, Optical Disks.
Input – Output Organization Accessing I/O devices, Direct Memory Access and DMA controller, Interrupts and Interrupt Controllers, Arbitration, Multilevel Bus Architecture, Interface circuits – Parallel and serial port. Features of PCI and PCI Express bus.
Unit III
16 AND 32 Microprocessors 80×86 Architecture, IA – 32 and IA – 64, Programming model, Concurrent operation of EU and BIU, Real mode addressing, Segmentation, addressing modes of 80×86, Instruction set of 80×86, I/O addressing in 80×86
Unit IV
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Unit V
Different Architectures VLIW Architecture, DSP Architecture, SoC architecture, MIPS Processor and programming
Text Books:
- V. Carl, G. Zvonko and S. G. Zaky, Computer organization, McGraw Hill, 1978.
- B. Brey and C. R. Sarma, The Intel microprocessors, Pearson Education, 2000.
Reference Books:
For the complete Syllabus, results, class timetable, and many other features kindly download the iStudy App
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For detail Syllabus of all other subjects of B.Tech 3rd Year 1st Sem Electrical & Electronics Engineering, visit EEE 3rd Year 1st Sem Syllabus Subjects.
For all B.Tech results, visit JNTUH B.Tech all years, and semester results from direct links.