Reply To: Computer Science and Information Technology (CS)- Doubts [GATE 2012]

  1. Please help me with the following problems:

    Q1. For inclusion to hold between two cache levels L1 and L2 in a multilevel cache hierarchy which of the following are necessary?
    1. L1 must be write through cache
    2. L2 must be write through cache
    3. Associativity of L1 must be greater than that of L2
    4. L2 cache must be atleast as large as L!

    a. 1,2,3,4 b.1,2,4 c.1,4 d.4 only

    Q2. For a disk with concentric circular tracks seek latency is not linearly proportional to seek distance due to
    a. unfair arm scheduling proecss
    b. higher capacity of tracks on the periphery of the platter
    c. arm starting and stopping inertia
    d. non-uniform distribution of request

    Q3. DRAM has memory cycle time of 64 ns. it has to be refreshed 100 times per ns and each refresh takes 100ns. What percentage of memory cycle is used for refreshing?
    a. 10 b.6.4 c.1 d.0.64

    Q4. Refreshing rate of DRAM is in the range of
    a. 3ms b.2ms c.50ms d.500ms

    Thank you.