Digital Electronics Syllabus for B.Tech 3rd sem is covered here. This gives the details about credits, number of hours and other details along with reference books for the course.<\/p>\n
The detailed syllabus for Digital Electronics B.Tech (R13) thirdsem is as follows<\/p>\n
OBJECTIVES:<\/strong><\/p>\n UNIT I : MINIMIZATION TECHNIQUES AND LOGIC GATES<\/strong> \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 [9 hours]<\/p>\n Minimization Techniques: Boolean postulates and laws \u2013 De-Morgan\u201fs Theorem – Principle of Duality – Boolean expression – Minimization of Boolean expressions \u2013\u2013 Minterm \u2013 Maxterm – Sum of Products (SOP) \u2013 Product of Sums (POS) \u2013 Karnaugh map Minimization \u2013 Don\u201ft care conditions \u2013 Quine – Mc Cluskey method of minimization. Logic Gates: AND, OR, NOT, NAND, NOR, Exclusive\u2013OR and Exclusive\u2013NOR Implementations of Logic Functions using gates, NAND\u2013NOR implementations \u2013 Multi\u00a0level gate implementations- Multi output gate implementations. TTL and CMOS Logic and their characteristics \u2013 Tristate gates<\/p>\n UNIT II : COMBINATIONAL CIRCUITS<\/strong> \u00a0 \u00a0\u00a0[9 hours]<\/p>\n Design procedure \u2013 Half adder \u2013 Full Adder \u2013 Half subtractor \u2013 Full subtractor \u2013 Parallel binary adder, parallel binary Subtractor \u2013 Fast Adder – Carry Look Ahead adder \u2013 Serial Adder\/Subtractor – BCD adder \u2013 Binary Multiplier \u2013 Binary Divider – Multiplexer\/ Demultiplexer \u2013 decoder – encoder \u2013 parity checker \u2013 parity generators \u2013 code converters – Magnitude Comparator.<\/p>\n UNIT III : SEQUENTIAL CIRCUITS<\/strong> \u00a0 \u00a0 \u00a0\u00a0[9 hours]<\/p>\n Latches, Flip-flops – SR, JK, D, T, and Master-Slave \u2013 Characteristic table and equation \u2013Application table \u2013 Edge triggering \u2013 Level Triggering \u2013 Realization of one flip flop using other flip flops \u2013 serial adder\/subtractor- Asynchronous Ripple or serial counter \u2013 Asynchronous Up\/Down counter – Synchronous counters \u2013 Synchronous Up\/Down counters \u2013 Programmable counters \u2013 Design of Synchronous counters: state diagram- State table \u2013State minimization \u2013State assignment – Excitation table and maps-Circuit implementation – Modulo\u2013n counter, Registers \u2013 shift registers – Universal shift registers \u2013 Shift register counters \u2013 Ring counter \u2013 Shift counters – Sequence generators.<\/p>\n\n