{"id":56781,"date":"2023-08-28T17:03:16","date_gmt":"2023-08-28T17:03:16","guid":{"rendered":"https:\/\/www.inspirenignite.com\/anna-university\/cec337-dsp-architecture-and-programming-syllabus-for-ete-2021-regulation-professional-elective-ii\/"},"modified":"2023-08-28T17:03:16","modified_gmt":"2023-08-28T17:03:16","slug":"cec337-dsp-architecture-and-programming-syllabus-for-ete-2021-regulation-professional-elective-ii","status":"publish","type":"post","link":"https:\/\/www.inspirenignite.com\/anna-university\/cec337-dsp-architecture-and-programming-syllabus-for-ete-2021-regulation-professional-elective-ii\/","title":{"rendered":"CEC337: DSP Architecture and Programming syllabus for ETE 2021 regulation (Professional Elective-II)"},"content":{"rendered":"

DSP Architecture and Programming detailed syllabus for Electronics & Telecommunication Engineering (ETE) for 2021 regulation curriculum has been taken from the Anna Universities<\/a> official website and presented for the ETE students. For course code, course name, number of credits for a course and other scheme related information, do visit full semester subjects post given below. <\/p>\n

For Electronics & Telecommunication Engineering 5th Sem scheme and its subjects, do visit ETE 5th Sem 2021 regulation scheme<\/a>. For Professional Elective-II scheme and its subjects refer to ETE Professional Elective-II syllabus scheme<\/a>. The detailed syllabus of dsp architecture and programming is as follows. <\/p>\n

Course Objectives:<\/h4>\n

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Unit I<\/h4>\n

ARCHITECTURES FOR PROGRAMMABLE DSP PROCESSORS
\nBasic Architectural features, DSP Computational building blocks, Bus architecture and memory, Data addressing capabilities, Address generation Unit, Programmability and program execution, Speed issues, Features for external interfacing\n<\/p>\n

Unit II<\/h4>\n

TMS 320C5 X PROGRAMMABLE DSP PROCESSOR
\nArchitecture of TMS 320 C54 xx DSP processors, Addressing modes – Assembly language Instructions -Memory space, interrupts, and pipeline operation of TMS 320 C54 xx DSP Processor, On-Chip peripherals, Block Diagram of TMS 320 C 54xx DSP starter kit\n<\/p>\n

Unit III<\/h4>\n

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Unit IV<\/h4>\n

IMPLEMENTATION OF DSP ALGORITHMS
\nDSP Development system, On-chip, and On-board peripherals of C54xx and C67xx DSP development boards, Code Composer Studio (CCS) and support files, Implementation of Conventional FIR, IIR, and Adaptive filters in TMS 320 C 54xx\/TMS 320 C 67xx DSP processors for real-time DSP applications, Implementation of FFT algorithm for frequency analysis in real-time.\n<\/p>\n

Unit V<\/h4>\n

APPLICATIONS OF DSP PROCESSORS
\nVoice scrambling using filtering and modulation, Voice detection and reverse playback, Audio effects, Graphic Equalizer, Adaptive noise cancellation, DTMF signal detection, Speech thesis using LPC, Automatic speaker recognition\n<\/p>\n

Practical Exercises<\/h4>\n
    \n
  1. Real-Time Sine Wave Generation<\/li>\n
  2. Programming examples using C, Assembly and linear assembly<\/li>\n
  3. Implementation of moving average filter<\/li>\n
  4. FIR implementation with a Pseudorandom noise sequence as input to a filter<\/li>\n
  5. Fixed point implementation of IIR filter<\/li>\n
  6. FFT of Real-Time input signal<\/li>\n<\/ol>\n

    HARDWARE & SOFTWARE SUPPORT TOOLS:<\/i><\/p>\n