{"id":55265,"date":"2023-08-28T07:13:03","date_gmt":"2023-08-28T07:13:03","guid":{"rendered":"https:\/\/www.inspirenignite.com\/anna-university\/ec3552-vlsi-and-chip-design-syllabus-for-ete-2021-regulation\/"},"modified":"2023-08-28T07:13:03","modified_gmt":"2023-08-28T07:13:03","slug":"ec3552-vlsi-and-chip-design-syllabus-for-ete-2021-regulation","status":"publish","type":"post","link":"https:\/\/www.inspirenignite.com\/anna-university\/ec3552-vlsi-and-chip-design-syllabus-for-ete-2021-regulation\/","title":{"rendered":"EC3552: VLSI and Chip Design syllabus for ETE 2021 regulation"},"content":{"rendered":"<p align=\"justify\">VLSI and Chip Design detailed syllabus for Electronics &amp; Telecommunication Engineering (ETE) for 2021 regulation curriculum has been taken from the <a class=\"rank-math-link\" href=\"https:\/\/cac.annauniv.edu\/\" style=\"color: inherit\" target=\"_blank\" rel=\"noopener\">Anna University<\/a> official website and presented for the ETE students. For course code, course name, number of credits for a course and other scheme related information,  do visit full semester subjects post given below. <\/p>\n<p align=\"justify\">For Electronics &amp; Telecommunication Engineering 5th Sem scheme and its subjects, do visit <a class=\"rank-math-link\" href=\"..\/ete-5th-sem-syllabus-2021-regulation\">ETE 5th Sem 2021 regulation scheme<\/a>. The detailed syllabus of vlsi and chip design is as follows. <\/p>\n<p><h4>Course Objectives:<\/h4>\n<h4 id=\"istudy\" style=\"text-align:center\"><a class=\"rank-math-link\" href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" style=\"color: inherit\" target=\"_blank\" rel=\"noopener\">Download the iStudy App for all syllabus and other updates.<\/a><br \/><a class=\"rank-math-link\" href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy&amp;pcampaignid=pcampaignidMKT-Other-global-all-co-prtnr-py-PartBadge-Mar2515-1\" target=\"_blank\" rel=\"noopener\"><img decoding=\"async\" src=\"https:\/\/play.google.com\/intl\/en_us\/badges\/static\/images\/badges\/en_badge_web_generic.png\" alt=\"Get it on Google Play\" style=\"height:65px;text-align:center\"><\/a><\/h4>\n<p><h4>Unit I<\/h4>\n<p>MOS TRANSISTOR PRINCIPLES<br \/>\nMOS logic families (NMOS and CMOS), Ideal and Non Ideal IV Characteristics, CMOS devices. MOS(FET) Transistor Characteristic under Static and Dynamic Conditions, Technology Scaling, power consumption\n<\/p>\n<p><h4>Unit II<\/h4>\n<p>COMBINATIONAL LOGIC CIRCUITS<br \/>\nPropagation Delays, stick diagram, Layout diagrams, Examples of combinational logic design, Elmore\u2019s constant, Static Logic Gates,Dynamic Logic Gates, Pass Transistor Logic, Power Dissipation, Low Power Design principles.\n<\/p>\n<p><h4>Unit III<\/h4>\n<h4 id=\"istudy\" style=\"text-align:center\"><a class=\"rank-math-link\" href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" style=\"color: inherit\" target=\"_blank\" rel=\"noopener\">Download the iStudy App for all syllabus and other updates.<\/a><br \/><a class=\"rank-math-link\" href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy&amp;pcampaignid=pcampaignidMKT-Other-global-all-co-prtnr-py-PartBadge-Mar2515-1\" target=\"_blank\" rel=\"noopener\"><img decoding=\"async\" src=\"https:\/\/play.google.com\/intl\/en_us\/badges\/static\/images\/badges\/en_badge_web_generic.png\" alt=\"Get it on Google Play\" style=\"height:65px;text-align:center\"><\/a><\/h4>\n<p><h4>Unit IV<\/h4>\n<p>INTERCONNECT , MEMORY ARCHITECTURE AND ARITHMETIC<br \/>\nCIRCUITS<br \/>\nInterconnect Parameters &#8211; Capacitance, Resistance, and Inductance, Electrical WireModels, Sequential digital circuits: adders, multipliers, comparators, shift registers. Logic Implementation using Programmable Devices (ROM, PLA, FPGA), Memory Architecture and Building Blocks,Memory Core and Memory Peripherals Circuitry\n<\/p>\n<p><h4>Unit V<\/h4>\n<p>ASIC DESIGN AND TESTING<br \/>\nIntroduction to wafer to chip fabrication process flow. Microchip design process &amp; issues in test and verification of complex chips, embedded cores and SOCs, Fault models, Test coding. ASIC Design Flow, Introduction to ASICs, Introduction to test benches, Writing test benches in Verilog HDL, Automatic test pattern generation, Design for testability, Scan design: Test interface and boundary scan.\n<\/p>\n<p><h4>Course Outcomes:<\/h4>\n<p>Upon successful completion of the course the student will be able to<\/p>\n<ol>\n<li>In depth knowledge of MOS technology<\/li>\n<li>Understand Combinational Logic Circuits and Design Principles<\/li>\n<li>Understand Sequential Logic Circuits and Clocking Strategies<\/li>\n<li>Understand Memory architecture and building blocks<\/li>\n<li>Understand the ASIC Design Process and Testing.<\/li>\n<\/ol>\n<p><h4>Text Books:<\/h4>\n<h4 id=\"istudy\" style=\"text-align:center\"><a class=\"rank-math-link\" href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" style=\"color: inherit\" target=\"_blank\" rel=\"noopener\">Download the iStudy App for all syllabus and other updates.<\/a><br \/><a class=\"rank-math-link\" href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy&amp;pcampaignid=pcampaignidMKT-Other-global-all-co-prtnr-py-PartBadge-Mar2515-1\" target=\"_blank\" rel=\"noopener\"><img decoding=\"async\" src=\"https:\/\/play.google.com\/intl\/en_us\/badges\/static\/images\/badges\/en_badge_web_generic.png\" alt=\"Get it on Google Play\" style=\"height:65px;text-align:center\"><\/a><\/h4>\n<p><h4>Reference Books:<\/h4>\n<ol>\n<li>D.A. Hodges and H.G. Jackson, Analysis and Design of Digital Integrated Circuits, International Student Edition, McGraw Hill 1983<\/li>\n<li>P. Rashinkar, Paterson and L. Singh, &#8220;System-on-a-Chip Verification-Methodology and Techniques&#8221;, Kluwer Academic Publishers,2001<\/li>\n<li>SamihaMourad and YervantZorian, \u201cPrinciples of Testing Electronic Systems\u201d, Wiley 2000<\/li>\n<li>M. Bushnell and V. D. Agarwal, &#8220;Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits&#8221;, Kluwer Academic Publishers,2000<\/li>\n<\/li>\n<\/ol>\n<p align=\"justify\">For detailed syllabus of all other subjects of Electronics &amp; Telecommunication Engineering, 2021 regulation curriculum do visit <a class=\"rank-math-link\" href=\"..\/category\/ete+5th-sem\">ETE 5th Sem subject syllabuses for 2021 regulation<\/a>. <\/p>\n<p align=\"justify\">For all Electronics &amp; Telecommunication Engineering results, visit <a class=\"rank-math-link\" href=\"https:\/\/www.inspirenignite.com\/anna-university\/anna-university-results\/\">Anna University ETE all semester results<\/a> direct link. <\/p>\n","protected":false},"excerpt":{"rendered":"<p>VLSI and Chip Design detailed syllabus for Electronics &amp; Telecommunication Engineering (ETE) for 2021 regulation curriculum has been taken from the Anna University official website and presented for the ETE [&hellip;]<\/p>\n","protected":false},"author":2297,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_bbp_topic_count":0,"_bbp_reply_count":0,"_bbp_total_topic_count":0,"_bbp_total_reply_count":0,"_bbp_voice_count":0,"_bbp_anonymous_reply_count":0,"_bbp_topic_count_hidden":0,"_bbp_reply_count_hidden":0,"_bbp_forum_subforum_count":0,"footnotes":""},"categories":[48,147],"tags":[],"class_list":["post-55265","post","type-post","status-publish","format-standard","hentry","category-5th-sem","category-ete"],"_links":{"self":[{"href":"https:\/\/www.inspirenignite.com\/anna-university\/wp-json\/wp\/v2\/posts\/55265","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.inspirenignite.com\/anna-university\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.inspirenignite.com\/anna-university\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/anna-university\/wp-json\/wp\/v2\/users\/2297"}],"replies":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/anna-university\/wp-json\/wp\/v2\/comments?post=55265"}],"version-history":[{"count":0,"href":"https:\/\/www.inspirenignite.com\/anna-university\/wp-json\/wp\/v2\/posts\/55265\/revisions"}],"wp:attachment":[{"href":"https:\/\/www.inspirenignite.com\/anna-university\/wp-json\/wp\/v2\/media?parent=55265"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/anna-university\/wp-json\/wp\/v2\/categories?post=55265"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/anna-university\/wp-json\/wp\/v2\/tags?post=55265"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}