{"id":53617,"date":"2023-04-08T06:08:31","date_gmt":"2023-04-08T06:08:31","guid":{"rendered":"https:\/\/www.inspirenignite.com\/anna-university\/ec3552-vlsi-and-chip-design-syllabus-for-ece-2021-regulation\/"},"modified":"2023-04-08T06:08:31","modified_gmt":"2023-04-08T06:08:31","slug":"ec3552-vlsi-and-chip-design-syllabus-for-ece-2021-regulation","status":"publish","type":"post","link":"https:\/\/www.inspirenignite.com\/anna-university\/ec3552-vlsi-and-chip-design-syllabus-for-ece-2021-regulation\/","title":{"rendered":"EC3552: VLSI and Chip Design syllabus for ECE 2021 regulation"},"content":{"rendered":"

VLSI and Chip Design detailed syllabus for Electronics & Communication Engineering (ECE) for 2021 regulation curriculum has been taken from the Anna University<\/a> official website and presented for the ECE students. For course code, course name, number of credits for a course and other scheme related information, do visit full semester subjects post given below. <\/p>\n

For Electronics & Communication Engineering 5th Sem scheme and its subjects, do visit ECE 5th Sem 2021 regulation scheme<\/a>. The detailed syllabus of vlsi and chip design is as follows. <\/p>\n

VLSI and Chip Design<\/title><\/p>\n<h4>Course Objectives:<\/h4>\n<h4 id=\"istudy\" style=\"text-align:center\"><a class=\"rank-math-link\" href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" style=\"color: inherit\" target=\"_blank\" rel=\"noopener\">Download the iStudy App for all syllabus and other updates.<\/a><br \/><a class=\"rank-math-link\" href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy&pcampaignid=pcampaignidMKT-Other-global-all-co-prtnr-py-PartBadge-Mar2515-1\" target=\"_blank\" rel=\"noopener\"><img decoding=\"async\" src=\"https:\/\/play.google.com\/intl\/en_us\/badges\/static\/images\/badges\/en_badge_web_generic.png\" alt=\"Get it on Google Play\" style=\"height:65px;text-align:center\"><\/a><\/h4>\n<h4>Unit I<\/h4>\n<p> <strong>MOS TRANSISTOR PRINCIPLES 9<\/strong> MOS logic families (NMOS and CMOS), Ideal and Non Ideal IV Characteristics, CMOS devices. MOS(FET) Transistor Characteristic under Static and Dynamic Conditions, Technology Scaling, power consumption<\/p>\n<h4>Unit II<\/h4>\n<h4 id=\"istudy\" style=\"text-align:center\"><a class=\"rank-math-link\" href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" style=\"color: inherit\" target=\"_blank\" rel=\"noopener\">Download the iStudy App for all syllabus and other updates.<\/a><br \/><a class=\"rank-math-link\" href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy&pcampaignid=pcampaignidMKT-Other-global-all-co-prtnr-py-PartBadge-Mar2515-1\" target=\"_blank\" rel=\"noopener\"><img decoding=\"async\" src=\"https:\/\/play.google.com\/intl\/en_us\/badges\/static\/images\/badges\/en_badge_web_generic.png\" alt=\"Get it on Google Play\" style=\"height:65px;text-align:center\"><\/a><\/h4>\n<h4>Unit III<\/h4>\n<p> <strong>SEQUENTIAL LOGIC CIRCUITS AND CLOCKING STRATEGIES 9<\/strong> Static Latches and Registers, Dynamic Latches and Registers, Pipelines, Nonbistable Sequential Circuits.Timing classification of Digital Systems, Synchronous Design, Self-Timed Circuit Design .<\/p>\n<h4>Unit IV<\/h4>\n<h4 id=\"istudy\" style=\"text-align:center\"><a class=\"rank-math-link\" href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" style=\"color: inherit\" target=\"_blank\" rel=\"noopener\">Download the iStudy App for all syllabus and other updates.<\/a><br \/><a class=\"rank-math-link\" href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy&pcampaignid=pcampaignidMKT-Other-global-all-co-prtnr-py-PartBadge-Mar2515-1\" target=\"_blank\" rel=\"noopener\"><img decoding=\"async\" src=\"https:\/\/play.google.com\/intl\/en_us\/badges\/static\/images\/badges\/en_badge_web_generic.png\" alt=\"Get it on Google Play\" style=\"height:65px;text-align:center\"><\/a><\/h4>\n<h4>Unit V<\/h4>\n<p> <strong>ASIC DESIGN AND TESTING 9<\/strong> Introduction to wafer to chip fabrication process flow. Microchip design process & issues in test and verification of complex chips, embedded cores and SOCs, Fault models, Test coding. ASIC Design Flow, Introduction to ASICs, Introduction to test benches, Writing test benches in Verilog HDL, Automatic test pattern generation, Design for testability, Scan design: Test interface and boundary scan.<\/p>\n<h4>Course Outcomes:<\/h4>\n<h4 id=\"istudy\" style=\"text-align:center\"><a class=\"rank-math-link\" href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" style=\"color: inherit\" target=\"_blank\" rel=\"noopener\">Download the iStudy App for all syllabus and other updates.<\/a><br \/><a class=\"rank-math-link\" href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy&pcampaignid=pcampaignidMKT-Other-global-all-co-prtnr-py-PartBadge-Mar2515-1\" target=\"_blank\" rel=\"noopener\"><img decoding=\"async\" src=\"https:\/\/play.google.com\/intl\/en_us\/badges\/static\/images\/badges\/en_badge_web_generic.png\" alt=\"Get it on Google Play\" style=\"height:65px;text-align:center\"><\/a><\/h4>\n<h4>Text Books:<\/h4>\n<ol>\n<li>Jan D Rabaey, Anantha Chandrakasan, Digital Integrated Circuits: A Design Perspective, PHI, 2016.(Units II, III and IV).<\/li>\n<li>Neil H E Weste, Kamran Eshranghian, Principles of CMOS VLSI Design: A System Perspective, Addison Wesley, 2009.( Units – I, IV).<\/li>\n<li>Michael J Smith , Application Specific Integrated Circuits, Addison Wesley, (Unit – V)<\/li>\n<li>Samir Palnitkar, Verilog HDL:A guide to Digital Design and Synthesis, Second Edition, Pearson Education,2003.(Unit – V)<\/li>\n<li>Parag K.Lala, Digital Circuit Testing and Testability, Academic Press, 1997, (Unit – V)<\/li>\n<\/ol>\n<h4>Reference Books:<\/h4>\n<ol>\n<li>D.A. Hodges and H.G. Jackson, Analysis and Design of Digital Integrated Circuits, International Student Edition, McGraw Hill 1983<\/li>\n<li>P. Rashinkar, Paterson and L. Singh, “System-on-a-Chip Verification-Methodology and Techniques”, Kluwer Academic Publishers,2001<\/li>\n<li>SamihaMourad and YervantZorian, Principles of Testing Electronic Systems, Wiley 2000<\/li>\n<li>M. Bushnell and V. D. Agarwal, “Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits”, Kluwer Academic Publishers,2000<\/li>\n<\/ol>\n<p align=\"justify\">For detailed syllabus of all other subjects of Electronics & Communication Engineering, 2021 regulation curriculum do visit <a class=\"rank-math-link\" href=\"..\/category\/ece+5th-sem\">ECE 5th Sem subject syllabuses for 2021 regulation<\/a>. <\/p>\n<p align=\"justify\">For all Electronics & Communication Engineering results, visit <a class=\"rank-math-link\" href=\"https:\/\/www.inspirenignite.com\/anna-university\/anna-university-results\/\">Anna University ECE all semester results<\/a> direct link. <\/p>\n","protected":false},"excerpt":{"rendered":"<p>VLSI and Chip Design detailed syllabus for Electronics & Communication Engineering (ECE) for 2021 regulation curriculum has been taken from the Anna University official website and presented for the ECE […]<\/p>\n","protected":false},"author":2297,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_bbp_topic_count":0,"_bbp_reply_count":0,"_bbp_total_topic_count":0,"_bbp_total_reply_count":0,"_bbp_voice_count":0,"_bbp_anonymous_reply_count":0,"_bbp_topic_count_hidden":0,"_bbp_reply_count_hidden":0,"_bbp_forum_subforum_count":0,"footnotes":""},"categories":[48,71],"tags":[],"class_list":["post-53617","post","type-post","status-publish","format-standard","hentry","category-5th-sem","category-ece"],"_links":{"self":[{"href":"https:\/\/www.inspirenignite.com\/anna-university\/wp-json\/wp\/v2\/posts\/53617","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.inspirenignite.com\/anna-university\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.inspirenignite.com\/anna-university\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/anna-university\/wp-json\/wp\/v2\/users\/2297"}],"replies":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/anna-university\/wp-json\/wp\/v2\/comments?post=53617"}],"version-history":[{"count":0,"href":"https:\/\/www.inspirenignite.com\/anna-university\/wp-json\/wp\/v2\/posts\/53617\/revisions"}],"wp:attachment":[{"href":"https:\/\/www.inspirenignite.com\/anna-university\/wp-json\/wp\/v2\/media?parent=53617"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/anna-university\/wp-json\/wp\/v2\/categories?post=53617"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/anna-university\/wp-json\/wp\/v2\/tags?post=53617"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}