{"id":32693,"date":"2021-05-21T07:31:18","date_gmt":"2021-05-21T07:31:18","guid":{"rendered":"https:\/\/www.inspirenignite.com\/anna-university\/ec5611-vlsi-laboratory-syllabus-for-ece-6th-sem-2019-regulation-anna-university\/"},"modified":"2021-05-21T07:31:18","modified_gmt":"2021-05-21T07:31:18","slug":"ec5611-vlsi-laboratory-syllabus-for-ece-6th-sem-2019-regulation-anna-university","status":"publish","type":"post","link":"https:\/\/www.inspirenignite.com\/anna-university\/ec5611-vlsi-laboratory-syllabus-for-ece-6th-sem-2019-regulation-anna-university\/","title":{"rendered":"EC5611: VLSI Laboratory Syllabus for ECE 6th Sem 2019 Regulation Anna University"},"content":{"rendered":"

VLSI Laboratory detailed syllabus for Electronics & Communication Engineering (ECE) for 2019 regulation curriculum has been taken from the Anna Universities<\/a> official website and presented for the ECE students. For course code, course name, number of credits for a course and other scheme related information, do visit full semester subjects post given below. <\/p>\n

For Electronics & Communication Engineering 6th Sem scheme and its subjects, do visit ECE 6th Sem 2019 regulation scheme<\/a>. The detailed syllabus of vlsi laboratory is as follows. <\/p>\n

VLSI Laboratory<\/title><\/p>\n<h4>Course Objective:<\/h4>\n<p align=\"justify\">\n<ul>\n<li>To introduce the relevance of this course to the existing technology through demonstrations, case studies, simulations, contributions of scientist, national\/international policies with a futuristic vision along with socio-economic impact and issues<\/li>\n<li>To learn the Hardware Description Language (Verilog\/VHDL)<\/li>\n<li>To learn the fundamental principles of VLSI circuit design in digital and analog domain<\/li>\n<li>To familiarize fusing of logical modules on FPGAs<\/li>\n<li>To provide hands on design experience with hardware\/software based embedded system.<\/li>\n<\/ul>\n<h4>Digital and Analog Experiments<\/h4>\n<p align=\"justify\">\n<p><i>I Digital Experiments – FPGA BASED EXPERIMENTS:<\/i>\n <\/p>\n<ol>\n<li>Design and simulation of Full adder and full subtractor<\/li>\n<li>Design and simulation of multiplexer, Decoder and 4 bit comparator<\/li>\n<li>Design and simulation of 8 bit adder<\/li>\n<li>HDL based design entry and simulation of Ripple counter, synchronous counter and BCD counter<\/li>\n<li>Design and simulation of simple state machines<\/li>\n<li>4 bit multiplier design and simulation using HDL<\/li>\n<li>Synthesis, P&R and post P&R simulation of the components simulated in (1-6) above. Critical paths and static timing analysis results to be identified. Identify and verify possible conditions under which the blocks will fail to work correctly.<\/li>\n<li>Hardware fusing and testing of each of the blocks simulated in (1-6). Use of either chipscope feature (Xilinx) or the signal tap feature (Altera) is a must. Invoke the PLL and demonstrate the use of the PLL module for clock generation in FPGAs..<\/li>\n<\/ol>\n<p> <i>II Analog \/ IC Design Experiments<\/i> (Based on Cadence\/Any other equivalent SPICE Circuit Simulator and FPAA based experiments)<\/p>\n<ol>\n<li>Design and simulation of a simple five transistor differential amplifier – Measure gain, ICMR and CMRR<\/li>\n<li>Layout generation, parasitic extraction and resimulation of the five transistor differential amplifier<\/li>\n<li>Synthesis and standard cell based design of circuits simulated in 9 above. Identification of critical paths, power consumption<\/li>\n<li>For experiment 11 above, P and R, Power and clock routing and post P and R simulation<\/li>\n<li>Analysis of results of static timing analysis<\/li>\n<\/ol>\n<p><i>FPAA Based Experiments:<\/i>\n <\/p>\n<ol>\n<li>Design, Simulate and implement an inverting gain amplifier, low pass, high pass filters and full wave rectifier. Analyze the frequency response of filters<\/li>\n<li>Design and Implement a circuit which introduces noise tone to the audio and then bring the original audio by removing the noise tone<\/li>\n<\/ol>\n<h4>Course Outcome:<\/h4>\n<p align=\"justify\">\n At the end of the course, the student should be able to<\/p>\n<ol>\n<li>Ability to implement digital circuits in FPGA using HDL<\/li>\n<li>Ability to realize digital circuits satisfying timing and area constraints<\/li>\n<li>Ability to Synthesize, Place and Route the digital IPs<\/li>\n<li>Ability to design, simulate and extract the layout of Analog IC Blocks using EDA tools<\/li>\n<li>Ability to comprehend and appreciate the significance and role of this course in the present contemporary world<\/li>\n<\/ol>\n<p align=\"justify\">For detailed syllabus of all other subjects of Electronics & Communication Engineering, 2019 regulation curriculum do visit <a class=\"rank-math-link\" href=\"..\/category\/ece+6th-sem\">ECE 6th Sem subject syllabuses for 2019 regulation<\/a>. <\/p>\n<p align=\"justify\">For all Electronics & Communication Engineering results, visit <a class=\"rank-math-link\" href=\"https:\/\/www.inspirenignite.com\/anna-university\/anna-university-results\/\">Anna University ECE all semester results<\/a> direct link. <\/p>\n","protected":false},"excerpt":{"rendered":"<p>VLSI Laboratory detailed syllabus for Electronics & Communication Engineering (ECE) for 2019 regulation curriculum has been taken from the Anna Universities official website and presented for the ECE students. For […]<\/p>\n","protected":false},"author":2297,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_bbp_topic_count":0,"_bbp_reply_count":0,"_bbp_total_topic_count":0,"_bbp_total_reply_count":0,"_bbp_voice_count":0,"_bbp_anonymous_reply_count":0,"_bbp_topic_count_hidden":0,"_bbp_reply_count_hidden":0,"_bbp_forum_subforum_count":0,"footnotes":""},"categories":[49,71],"tags":[],"class_list":["post-32693","post","type-post","status-publish","format-standard","hentry","category-6th-sem","category-ece"],"_links":{"self":[{"href":"https:\/\/www.inspirenignite.com\/anna-university\/wp-json\/wp\/v2\/posts\/32693","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.inspirenignite.com\/anna-university\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.inspirenignite.com\/anna-university\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/anna-university\/wp-json\/wp\/v2\/users\/2297"}],"replies":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/anna-university\/wp-json\/wp\/v2\/comments?post=32693"}],"version-history":[{"count":0,"href":"https:\/\/www.inspirenignite.com\/anna-university\/wp-json\/wp\/v2\/posts\/32693\/revisions"}],"wp:attachment":[{"href":"https:\/\/www.inspirenignite.com\/anna-university\/wp-json\/wp\/v2\/media?parent=32693"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/anna-university\/wp-json\/wp\/v2\/categories?post=32693"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/anna-university\/wp-json\/wp\/v2\/tags?post=32693"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}