{"id":19108,"date":"2019-12-10T05:45:16","date_gmt":"2019-12-10T05:45:16","guid":{"rendered":"https:\/\/www.inspirenignite.com\/anna-university\/vlsi-design-laboratory-ece-6th-sem-syllabus-for-be-2017-regulation-anna-univ\/"},"modified":"2019-12-10T05:45:16","modified_gmt":"2019-12-10T05:45:16","slug":"vlsi-design-laboratory-ece-6th-sem-syllabus-for-be-2017-regulation-anna-univ","status":"publish","type":"post","link":"https:\/\/www.inspirenignite.com\/anna-university\/vlsi-design-laboratory-ece-6th-sem-syllabus-for-be-2017-regulation-anna-univ\/","title":{"rendered":"Vlsi Design Laboratory Ece 6th Sem Syllabus for BE 2017 Regulation Anna Univ"},"content":{"rendered":"<p>Vlsi Design Laboratory detail syllabus for Electronics And Communication Engineering (Ece), 2017 regulation is taken from <a href=\"https:\/\/www.annauniv.edu\/\" target=\"_blank\" rel=\"noopener\">Anna University<\/a> official website and presented for students of Anna University. The details of the course are: course code (EC8661), Category (PC), Contact Periods\/week (4), Teaching hours\/week (0), Practical Hours\/week (0). The total course credits are 4.<\/p>\n<p>For all other ece 6th sem syllabus for be 2017 regulation anna univ you can visit <a href=\"..\/ece-6th-sem-syllabus-for-be-2017-regulation-anna-univ\">Ece 6th Sem syllabus for BE 2017 regulation Anna Univ Subjects<\/a>. The detail syllabus for vlsi design laboratory is as follows.&#8221;<\/p>\n<p><h4>Course Objective:<\/h4>\n<p>The student should be made:<\/p>\n<ul>\n<li>To learn Hardware Descriptive Language(Verilog\/VHDL)<\/li>\n<li>To learn the fundamental principles of VLSI circuit design in digital and analog domain<\/li>\n<li>To familiarize fusing of logical modules on FPGAs<\/li>\n<li>To provide hands on design experience with professional design (EDA) platforms<\/li>\n<\/ul>\n<p><h4>Experiments Part I:<\/h4>\n<p>Digital System Design using HDL and FPGA (24 Periods)<\/p>\n<ol>\n<li>Design an Adder (Min 8 Bit) using HDL. Simulate it using Xilinx\/Altera Software and implement by Xilinx\/Altera FPGA<\/li>\n<li>Design a Multiplier (4 Bit Min) using HDL. Simulate it using Xilinx\/Altera Software and implement by Xilinx\/Altera FPGA<\/li>\n<li>Design an ALU using HDL. Simulate it using Xilinx\/Altera Software and implement by Xilinx\/Altera FPGA<\/li>\n<li>Design a Universal Shift Register using HDL. Simulate it using Xilinx\/Altera Software and implement by Xilinx\/Altera FPGA<\/li>\n<li>Design Finite State Machine (Moore\/Mealy) using HDL. Simulate it using Xilinx\/Altera Software and implement by Xilinx\/Altera FPGA<\/li>\n<li>Design Memories using HDL. Simulate it using Xilinx\/Altera Software and implement by Xilinx\/Altera FPGA<\/li>\n<p>Compare pre synthesis and post synthesis simulation for experiments 1 to 6.\n<\/ol>\n<\/p>\n<p><i>Requirements:<\/i><br \/>\nXilinx ISE\/Altera Quartus\/ equivalent EDA Tools along with Xilinx\/Altera\/equivalent FPGA Boards\n<\/p>\n<p><h4>Experiments Part II:<\/h4>\n<p>Digital Circuit Design (24 Periods)<\/p>\n<ol>\n<li>Design and simulate a CMOS inverter using digital flow<\/li>\n<li>Design and simulate a CMOS Basic Gates and Flip-Flops<\/li>\n<li>Design and simulate a 4-bit synchronous counter using a Flip-Flops<\/li>\n<p>Manual\/Automatic Layout Generation and Post Layout Extraction for experiments 7 to 9<br \/>\nAnalyze the power, area and timing for experiments 7 to 9 by performing Pre Layout and Post Layout Simulations.\n<\/ol>\n<\/p>\n<p><h4>Experiments Part III:<\/h4>\n<p>Analog Circuit Design (12 Periods)<\/p>\n<ol>\n<li>Design and Simulate a CMOS Inverting Amplifier.<\/li>\n<p>Design and Simulate basic Common Source, Common Gate and Common Drain<\/p>\n<li>Amplifiers.<\/li>\n<p>Analyze the input impedance, output impedance, gain and bandwidth for experiments 10 and 11 by performing Schematic Simulations.<br \/>\nDesign and simulate simple 5 transistor differential amplifier. Analyze Gain,<\/p>\n<li>Bandwidth and CMRR by performing Schematic Simulations.<\/li>\n<\/ol>\n<p><i>Requirements:<\/i><br \/>\nCadence\/Synopsis\/ Mentor Graphics\/Tanner\/equivalent EDA Tools\n<\/p>\n<p><h4>Course Outcome:<\/h4>\n<p>At the end of the course, the student should be able to:<\/p>\n<ul>\n<li>Write HDL code for basic as well as advanced digital integrated circuit<\/li>\n<li>Import the logic modules into FPGA Boards<\/li>\n<li>Synthesize Place and Route the digital IPs<\/li>\n<li>Design, Simulate and Extract the layouts of Digital and Analog IC Blocks using EDA tools<\/li>\n<\/ul>\n<p><h4>List of Equipments for a Batch of 30 Students<\/h4>\n<p>S.NO\tEQUIPMENT\tREQUIRED<\/p>\n<ol>\n<li>Xilinx ISE\/Altera Quartus\/ equivalent EDA Tools\t10 User License<\/li>\n<li>Xilinx\/Altera\/equivalent FPGA Boards\t10 no<\/li>\n<li>Cadence\/Synopsis\/ Mentor Graphics\/Tanner\/equivalent EDA Tools\t10 User License<\/li>\n<li>Personal Computer\t30 no<\/li>\n<\/li>\n<\/ol>\n<p>For detail syllabus of all other subjects of BE Ece, 2017 regulation do visit <a href=\"..\/category\/ece+6th-sem\">Ece 6th Sem syllabus for 2017 Regulation<\/a>.<\/p>\n<p>Dont forget to <a href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" target=\"_blank\" rel=\"noopener\">download iStudy<\/a> for latest syllabus and results, class timetable and more.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Vlsi Design Laboratory detail syllabus for Electronics And Communication Engineering (Ece), 2017 regulation is taken from Anna University official website and presented for students of Anna University. The details of [&hellip;]<\/p>\n","protected":false},"author":2297,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_bbp_topic_count":0,"_bbp_reply_count":0,"_bbp_total_topic_count":0,"_bbp_total_reply_count":0,"_bbp_voice_count":0,"_bbp_anonymous_reply_count":0,"_bbp_topic_count_hidden":0,"_bbp_reply_count_hidden":0,"_bbp_forum_subforum_count":0,"footnotes":""},"categories":[49,71],"tags":[],"class_list":["post-19108","post","type-post","status-publish","format-standard","hentry","category-6th-sem","category-ece"],"_links":{"self":[{"href":"https:\/\/www.inspirenignite.com\/anna-university\/wp-json\/wp\/v2\/posts\/19108","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.inspirenignite.com\/anna-university\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.inspirenignite.com\/anna-university\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/anna-university\/wp-json\/wp\/v2\/users\/2297"}],"replies":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/anna-university\/wp-json\/wp\/v2\/comments?post=19108"}],"version-history":[{"count":0,"href":"https:\/\/www.inspirenignite.com\/anna-university\/wp-json\/wp\/v2\/posts\/19108\/revisions"}],"wp:attachment":[{"href":"https:\/\/www.inspirenignite.com\/anna-university\/wp-json\/wp\/v2\/media?parent=19108"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/anna-university\/wp-json\/wp\/v2\/categories?post=19108"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/anna-university\/wp-json\/wp\/v2\/tags?post=19108"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}